The present invention relates to a pattern synchronizing circuit and method for use with, for example, a digital error detector to produce from an input clock a reference pattern synchronized with an input pattern.
In general, a digital error in the output of a certain apparatus or transmission line having input thereinto a code signal is detected in such a manner as shown in FIG. 1. A test pattern generator 11 generates a test pattern P which repeats a bit pattern of a predetermined length, such as a pseudo-random binary sequence (PRBS) having a desired data bit cycle, and a test clock signal CK which rises substantially at the intermediate point of each data bit cycle of the test pattern P and has the same period as that of the data bit cycle. The test pattern P and the test clock signal CK are applied to a device under test 12 and a digital error detector 13. An output pattern P' of the device under test 12 is provided to the digital error detector 13. The test pattern P of one period is, for example, 2.sup.23 -1 bits in length. In the digital error detector 13 a test pattern synchronized with the input pattern P' is produced, as a reference pattern Pr, based on the test clock signal CK, and the reference pattern Pr and the output pattern P' from the device under test 12 are compared to detect a digital error in the latter.
FIG. 2 shows a conventional pattern synchronizing circuit disclosed in the present inventor's U.S. Pat. No. 4,878,233 for use in the digital error detector 13 to create the reference pattern Pr synchronized with the input pattern P'. The input pattern P' from a pattern input terminal 14 is applied to a re-timing circuit 15, which is formed by a D flip-flop and in which the input pattern P' is re-timed by the input clock signal CK which is provided via a variable delay circuit 17 from a clock input terminal 16. The input pattern thus re-timed is applied to an exclusive-OR circuit 19 in a digital error detector circuit 18, wherein it is compared with the reference pattern Pr from a reference pattern generator 21. The output of the exclusive-OR circuit 19 is applied to a gate 22, which is supplied with the output clock of the variable delay circuit 17. The exclusive-OR circuit 19 outputs a "1" or "0", depending on whether or not the logical values of the input patterns match each other. The output from the exclusive-OR circuit 19 is a NRZ waveform. In the gate 22 the NRZ waveform output is ANDed with the clock signal from the variable delay circuit 17, by which it is converted to a RZ waveform. When the input pattern from the re-timing circuit 15 does not match the reference pattern Pr, one pulse is output, as a digital error detected pulse, to a terminal 23 for each data bit cycle of the above-mentioned input pattern, and the detected pulse is applied to, for example, a high precision error rate detector (not shown).
The output clock signal of the variable delay circuit 17 is provided via an inhibit gate 24 to the reference pattern generator 21, which produces the reference pattern Pr, based on the clock signal. When the reference pattern is not synchronized with the input pattern, many digital error detected pulses are produced. The digital error detected pulses are supplied to a simple-structured error rate detector 25 which is formed by a frequency divider and by which the error rate is roughly measured. When the error rate is larger than 10.sup.-3, for instance, an inhibit gate control circuit 26 is caused to generate one inhibit pulse INH (which has a pulse width large enough to inhibit the input clock by one period), which is supplied to the inhibit gate 24, inhibiting the passage therethrough of one pulse of the input clock to delay the phase of the reference pattern Pr for one clock relative to the input pattern. Following this, the error rate is measured again and compared with the above-mentioned value 10.sup.-3, and if the former is larger than the latter, then another inhibit pulse INH is produced and the above-said operation is repeated. If the error rate is lower than 10.sup.-3, then no inhibit pulse INH is produced, but instead a pattern synchronization establishment signal is output via a terminal 27. This signal is used to indicate the establishment of synchronization of the input pattern with the reference pattern. The basic construction of such a conventional pattern synchronizing circuit is disclosed in U.S. Pat. No. 4,878,233, except re-timing of the input pattern.
As shown in FIG. 3, dead zones Z, which depend on the hold time t.sub.h and the setup time t.sub.s of the D flip-flop forming the re-timing circuit 15, exist before and after a data conversion node of the input pattern P' and when a jitter is present in the input pattern P', the dead zones Z become wider corresponding to the width of the jitter. In the case where the leading edge of the input clock CK which is supplied to the re-timing circuit 15 is within the dead zone z as depicted in FIG. 3, Rows A,B and C, the output of the re-timing circuit 15 does not become correct data and no output pattern is established, but instead a pattern containing a large error (an error rate above 10.sup.-3, for example) is usually output. In this instance, no pattern synchronization establishment signal would be produced, even if it is repeated to delay the reference pattern Pr for one cycle by inhibiting the passage of the input clock CK through the gate 22 with the inhibit pulse INH. Now, let Lp, Tc and Td represent the length of the test pattern, the period of the input clock CK and the time until it is decided whether the error rate is higher or lower than 10.sup.-3 after the application of the inhibit pulse INH, respectively. In the case where no pattern synchronization is established even after the lapse of a maximum time necessary for the pattern synchronization, Ts=Lp.times.(Tc+Td), an operator adjusts the variable delay circuit 17 to slightly delay the phase of the input clock CK from the state of Row A to the state of Row B in FIG. 3, for example. Where the pattern synchronization is not established yet after the time Ts elapses again, the phase of the input clock CK is delayed to the state of FIG. 3C, and in the example of FIG. 3, the phase of the input clock CK is further delayed to the state of Row D in FIG. 3. Thus, the leading edge of the input clock signal CK enters a phase difference allowable range AR between the dead zones Z of the input pattern, and hence the pattern synchronization can be established.
As will be seen from the above, no effective means has been available for definitely judging that the leading edge of the input clock signal CK is in the dead zone z of the input pattern; therefore, the prior art repeats adjusting the variable delay circuit for each lapse of a fixed time--this is a cumbersome and time-consuming operation. This operation must be performed not only at the start of a test but also when the frequency of the input clock is changed during test and the leading edge of the input clock enters the dead zone of the input pattern.